Timing circuit for locking a voltage controlled oscillator to a high frequency by use of low frequency quotients and resistor to switched capacitor matching
US11539328B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2020 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Dec 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03B2201/031
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Devices, systems, and methods for locking a voltage controlled oscillator (VCO) at a high frequency may include use of a VCO and an integrator, which generates and outputs a control signal to the VCO, based on an inverting signal and a reference signal. The control signal locks the VCO to a high frequency signal (FH). A frequency divider is coupled to the VCO, receives FH from the VCO, divides FH by a factor “F”, and outputs a low frequency signal (FL). A switched capacitor resistor circuit (SCRC) is coupled to the frequency divider and the integrator. The SCRC receives FL from the frequency divider and generates the inverting signal. An integrating capacitor is coupled across an inverting and an output terminal of op-amp in the integrator. The output of the op-amp provides an integrator signal, which may be (optionally) filtered to produce the control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.