Memory-network processor with programmable optimizations

US11544072B2 · kind B2 · utility

Assignee

• Coherent Logix, Incorporated · US

Inventors

• Michael B. Doerr · Weare Corner, US
• Carl S. Dobbs · Austin, US
• Michael B. Solka · Austin, US
• Michael R. Trocino · Austin, US
• Kenneth R. Faulkner · Austin, US
• Keith M. Bindloss · Irvine, US
• Sumeer Arya · Austin, US
• John Mark Beardslee · Menlo Park, US
• David A. Gibson · Austin, US

Key dates

• Filing date: Mar 16, 2021
• Grant date: Jan 3, 2023
• Expiry date: Mar 16, 2041

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. First and second address generator units may generate, based on different fields of the multi-part instruction, addresses from which to retrieve first and second data for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction. The execution units may perform operations using a single pipeline or multiple pipelines based on third and fourth fields of the multi-part instruction.