GPU networking using an integrated command processor
US11544121B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2017 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Nov 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2015/765
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods for generating network messages on a parallel processor are disclosed. A system includes at least a parallel processor, a general purpose processor, and a network interface unit. The parallel processor includes at least a plurality of compute units, a command processor, and a cache. A thread within a kernel executing on a compute unit of the parallel processor generates a network message and stores the network message and a corresponding indication in the cache. In response to detecting the indication of the network message in the cache, the command processor processes and conveys the network message to the network interface unit without involving the general purpose processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.