Method of fastening a semiconductor chip on a lead frame, and electronic component
US11545369B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2021 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Aug 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/0364
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic component includes a lead frame; a semiconductor chip arranged above the lead frame; and a connection layer sequence arranged between the lead frame and the semiconductor chip, wherein the connection layer sequence includes a first intermetallic layer including gold and indium or gold, indium and tin, a second intermetallic layer including indium and a titanium compound, indium and nickel, indium and platinum or indium and titanium, and a third intermetallic layer including indium and gold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.