Semiconductor wafer dicing process
US11545394B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2020 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Apr 11, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/68327
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer dicing process is disclosed for dicing a wafer into individual dies. Scribe lines are formed within a polymer coating to expose regions of wafer to form a pre-processed product. The pre-processed product within the chamber is plasma etched to remove the exposed regions of the wafer to separate the individual dies and form a processed product. A frame cover is then removed and the processed product, wafer frame and adhesive tape are exposed to an oxygen plasma within the chamber to partially remove an outermost region of the polymer coating, which is most heavily contaminated with fluorine, to leave a residual polymer coating on the individual dies and form a post-processed product. The residual polymer coating on the individual dies of the post-processed product is then removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.