Double sided embedded trace substrate
US11545435B2 · kind B2 · utility
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21Claims
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Key dates
| Filing date | Jun 5, 2020 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Jul 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/061
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some features pertain to a substrate that includes a first portion of the substrate including a first plurality of metal layers, a second portion of the substrate including a second plurality of metal layers, and a plurality of insulating layers configured to separate the first plurality of metal layers and the second plurality of metal layers. A first plurality of posts and a plurality of interconnects are coupled together such that the first plurality of posts and the plurality of interconnects couple the first portion of the substrate to the second portion of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.