Kuiwon Kang
28Patents
1h-index
26Co-inventors
53Inventor score
Filing activity: Mar 1, 2013 → Mar 1, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9679841B2 | Substrate and method of forming the same | Electricity | 10 | Active |
| US10622292B2 | High density interconnects in an embedded trace substrate (ETS) comprising a core layer | Electricity | 1 | Active |
| US11444019B2 | Package comprising a substrate with interconnect routing over solder resist layer and an integrated device coupled to the substrate and method for manufacturing the package | Electricity | 1 | Active |
| US10157824B2 | Integrated circuit (IC) package and package substrate comprising stacked vias | Electricity | 1 | Active |
| US10679919B2 | High thermal release interposer | Electricity | 1 | Active |
| US12354935B2 | Integrated circuit (IC) package substrate with embedded trace substrate (ETS) layer on a substrate, and related fabrication methods | Electricity | 0 | Active |
| US11545439B2 | Package comprising an integrated device coupled to a substrate through a cavity | Electricity | 0 | Active |
| US12362269B2 | Integrated circuit (IC) packages employing supplemental metal layer coupled to embedded metal traces in a die-side embedded trace substrate (ETS) layer, and related fabrication methods | Electricity | 0 | Active |
| US11552023B2 | Passive component embedded in an embedded trace substrate (ETS) | Electricity | 0 | Active |
| US9370097B2 | Package substrate with testing pads on fine pitch traces | Emerging Cross-Sectional Technologies | 0 | Active |
| US11791320B2 | Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods | Electricity | 0 | Active |
| US11527498B2 | Bump pad structure | Electricity | 0 | Active |
| US10971455B2 | Ground shield plane for ball grid array (BGA) package | Electricity | 0 | Active |
| US11552015B2 | Substrate comprising a high-density interconnect portion embedded in a core layer | Electricity | 0 | Active |
| US11605595B2 | Packages with local high-density routing region embedded within an insulating layer | Electricity | 0 | Active |
| US11437335B2 | Integrated circuit (IC) packages employing a thermal conductive package substrate with die region split, and related fabrication methods | Electricity | 0 | Active |
| US12424559B2 | Package with a substrate comprising embedded escape interconnects and surface escape interconnects | Electricity | 0 | Active |
| US11545435B2 | Double sided embedded trace substrate | Electricity | 0 | Active |
| US11776888B2 | Package with a substrate comprising protruding pad interconnects | Electricity | 0 | Active |
| US11637057B2 | Uniform via pad structure having covered traces between partially covered pads | Electricity | 0 | Active |
| US11764076B2 | Semi-embedded trace structure with partially buried traces | Electricity | 0 | Active |
| US10879158B2 | Split conductive pad for device terminal | Electricity | 0 | Active |
| US10804195B2 | High density embedded interconnects in substrate | Electricity | 0 | Active |
| US11404343B2 | Package comprising a substrate configured as a heat spreader | Electricity | 0 | Active |
| US11676905B2 | Integrated circuit (IC) package with stacked die wire bond connections, and related methods | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.