Semiconductor package
US11545440B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2020 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Jan 16, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a redistribution substrate including a first redistribution layer, a first molding member on the redistribution substrate, a second redistribution layer on an upper surface of the first molding member and having a redistribution pad, an electrical connection pad on an upper surface of a second molding member and electrically connected to the second redistribution layer, and a passivation layer on the second molding member and having an opening exposing at least a portion of the electrical connection pad. The electrical connection pad includes a conductor layer, including a first metal, and a contact layer on the conductor layer and including a second metal. The redistribution pad includes a third metal, different from the first metal and the second metal. The portion of the electrical connection pad, exposed by the opening, has a width greater than a width of the redistribution pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.