Interlocked redistribution layer interface for flip-chip integrated circuits
US11545450B2 · kind B2 · utility
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29Claims
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Key dates
| Filing date | Jul 16, 2020 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Sep 5, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/35121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This disclosure provides an integrated circuit device that includes a RDL that is interlocked with a bump (or “pillar”). The interlocked interface provides the contact RDL-bump interface with increased structural stability that can better withstand the thermal stresses associated with high performance devices IC devices. The interlock structure mitigates crack/delamination that occurs at the RDL-bump interface in large IC chips that are generally subjected to higher stresses during operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.