Patent · US Active

Method of dummy pattern layout

US11545484B2 · kind B2 · utility

0Cited by

4References

7Claims

0Family size

Assignee

UNITED MICROELECTRONICS CORP. · TW

Inventors

Jui-Fa Lu · Tainan, TW
Chien-Nan Lin · Gaodong, CN
Ching-Hua Yeh · Tainan, TW

Key dates

Filing date	Jan 15, 2021
Grant date	Jan 3, 2023
Priority date	—
Expiry date	May 10, 2041

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02P90/02
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A design method of a dummy pattern layout including the following steps is provided. An integrated circuit layout design including resistor elements is obtained via a computer. The locations of dummy conductive structures are configured, wherein the dummy conductive structures are aligned with the resistor elements. The locations of dummy support patterns are configured, wherein each of the dummy support patterns is configured between two adjacent dummy conductive structures, and each of the dummy conductive structures is equidistant from the dummy support patterns on both sides.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.