Deadtime optimization for GaN half-bridge and full-bridge switch topologies
US11545889B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2021 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Nov 29, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for deadtime optimization in a half-bridge switch or full-bridge switch wherein high-side and low-side switches comprise GaN transistors; a circuit for implementing the method; and a power switching system comprising a GaN half-bridge or a GaN full-bridge and a deadtime optimization system. The circuit comprises a drain current bump filter for generating a current charge output; and circuit elements for comparing the current charge output to a reference current charge Coss and generating a deadtime adjust signal. The deadtime adjust signal may be used to adjust deadtime to reduce or minimize deadtime, and deadtime losses, while avoiding cross-conduction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.