Traversing a variable delay line in a deterministic number of clock cycles
US11545987B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2019 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Dec 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a method includes initializing an input clock rotating register by sending a reset signal synchronized to an input clock signal and initializing an output clock rotating register by sending the reset signal synchronized to an output clock signal. The method further providing a data input synchronized to the output clock to a plurality of mux-flops. The output clock rotating register activates one of the plurality of mux-flops to receive the data input. The method further includes forwarding the data input via the one of the plurality of mux-flops to a multiplexer. The multiplexer has a selection input of the input clock rotating register. The method further includes selecting the data input as the output of the multiplexer to be a data output signal, such that the data output is synchronized with the input clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.