Patent · US Active

Driver device having an NMOS power transistor and a blocking circuit for stress test mode, and method of stress testing the driver device

US11549998B1 · kind B1 · utility

0Cited by

1References

22Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Carmelo Giunta · Munich, DE
Marcus Nuebling · Olching, DE
Steffen Thiele · Munich, DE

Key dates

Filing date	Jul 16, 2021
Grant date	Jan 10, 2023
Priority date	—
Expiry date	Jul 16, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/2642
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A driver device includes: a voltage terminal; a ground terminal; an output terminal; a first nMOS power transistor having a drain electrically connected to the voltage terminal, a source electrically connected to the output terminal, and a gate; an overvoltage protection circuit configured to limit a gate-to-source voltage of the first nMOS power transistor in a normal operating mode for the driver device; a pulldown circuit configured to force the first nMOS power transistor off in a stress test mode for the driver device; and a blocking circuit configured to block current flow from the output terminal to the ground terminal through the overvoltage protection circuit and the pulldown circuit in the stress test mode. A method of stress testing the driver device is also described.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.