Fused Multiply-Add operator for mixed precision floating-point numbers with correct rounding
US11550544B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 25, 2020 |
| Grant date | Jan 10, 2023 |
| Priority date | — |
| Expiry date | Jan 23, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49947
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fused multiply-add hardware operator comprising a multiplier receiving two multiplicands as floating-point numbers encoded in a first precision format; an alignment circuit associated with the multiplier configured to convert the result of the multiplication into a first fixed-point number; and an adder configured to add the first fixed-point number and an addition operand. The addition operand is a floating-point number encoded in a second precision format, and the operator comprises an alignment circuit associated with the addition operand, configured to convert the addition operand into a second fixed-point number of reduced dynamic range relative to the dynamic range of the addition operand, having a number of bits equal to the number of bits of the first fixed-point number, extended on both sides by at least the size of the mantissa of the addition operand; the adder configured to add the first and second fixed-point numbers without loss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.