Semiconductor memory devices and memory systems including the same
US11551775B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2021 |
| Grant date | Jan 10, 2023 |
| Priority date | — |
| Expiry date | May 6, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit and a control logic circuit to control the ECC circuit. The memory cell array includes memory cells and a normal cell region and a parity cell region The ECC circuit, in a normal mode, receives a main data, performs an ECC encoding on the main data to generate a parity data and stores the main data and the parity data in the normal cell region and the parity cell region. The ECC circuit, in a test mode, receives a test data including at least one error bit, stores the test data in one of the normal cell region and the parity cell region and performs an ECC decoding on the test data and one of the main data and the parity data to provide a decoding result data to an external device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.