Substrate comprising a high-density interconnect portion embedded in a core layer
US11552015B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2020 |
| Grant date | Jan 10, 2023 |
| Priority date | — |
| Expiry date | Jun 15, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/821
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate that includes a core layer comprising a first surface and a second surface, a plurality of core interconnects located in the core layer, a high-density interconnect portion located in the core layer, a first dielectric layer coupled to the first surface of the core layer, a first plurality of interconnects located in the first dielectric layer, a second dielectric layer coupled to the second surface of the core layer, and a second plurality of interconnects located in the second dielectric layer. The high-density interconnect portion includes a first redistribution dielectric layer and a first plurality of high-density interconnects located in the first redistribution dielectric layer. The high-density interconnect portion may provide high-density interconnects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.