Marking pattern in forming staircase structure of three-dimensional memory device
US11552025B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2021 |
| Grant date | Jan 10, 2023 |
| Priority date | — |
| Expiry date | Aug 17, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a semiconductor device includes a stack structure having insulating layers and conductor layers arranged alternatingly over a substrate along a vertical direction; and a marking pattern having interleaved layers over the substrate and neighboring the stack structure. The marking pattern includes a central marking structure located in a marking area. The central marking structure consists of interleaved layers and divides the marking area into a first marking sub-area and a second marking sub-area. A first pattern density of the first marking sub-area is higher than or equal to a second pattern density of the second marking sub-area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.