Chip packaging method and chip packaging structure
US11552028B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2020 |
| Grant date | Jan 10, 2023 |
| Priority date | — |
| Expiry date | Sep 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H9/02992
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for packaging a chip and a chip packaging structure. A passivation layer is provided on bonding pads of a wafer, a first metal bonding layer is formed on the passivation layer, and a second metal bonding layer is formed on a substrate. The substrate and the wafer are bonded via the first metal bonding layer and the second metal bonding layer, and are packaged as a whole. A first shielding layer is provided on the substrate, and the first shielding layer is in contact with the second metal bonding layer. After the wafer and the substrate are bonded, the wafer is subject to half-cutting to expose the first metal bonding layer. Then, the second shielding layer electrically connected to the first metal bonding layer is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.