Method and structure for forming stairs in three-dimensional memory devices

US11552097B2 · kind B2 · utility

Assignee

• YANGTZE MEMORY TECHNOLOGIES CO., LTD. · CN

Inventors

• Xinxin LIU · Beijing, CN
• Jingjing Geng · 红钢城街道, CN
• Zhu Yang · 红钢城街道, CN
• Chen Zuo · Beijing, CN
• Xiangning Wang · 红钢城街道, CN

Key dates

• Filing date: Dec 26, 2019
• Grant date: Jan 10, 2023
• Expiry date: Jan 11, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/50

Abstract

Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a memory stack having a plurality of stairs. Each stair may include interleaved one or more conductor layers and one or more dielectric layers. Each of the stairs includes one of the conductor layers on a top surface of the stair, the one of the conductor layers having (i) a bottom portion in contact with one of the dielectric layers, and (ii) a top portion exposed by the memory stack and in contact with the bottom portion. A lateral dimension of the top portion may be less than a lateral dimension of the bottom portion. An end of the top portion that may be facing away from the memory stack laterally exceeds the bottom portion by a distance.