Semiconductor device including data storage pattern with improved retention characteristics
US11552098B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2020 |
| Grant date | Jan 10, 2023 |
| Priority date | — |
| Expiry date | May 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A semiconductor device includes a lower structure; a stack structure including gate layers and interlayer insulating layers and having an opening; a vertical structure in the opening; a contact structure on the vertical structure; and a conductive line on the contact structure. The vertical structure includes an insulating core region, a channel semiconductor layer covering side and lower surfaces of the insulating core region, data storage patterns between the channel semiconductor layer and the gate layers and spaced apart from each other, a first dielectric layer, and a second dielectric layer. At least a portion of the first dielectric layer is between the data storage patterns and the gate layers, at least a portion of the second dielectric layer is between the data storage patterns and the channel semiconductor layer, and the insulating core region includes first convex portions having increased widths in regions facing the gate layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.