Source or drain structures with phosphorous and arsenic co-dopants

US11552169B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Anand S. Murthy · Beaverton, US
• Ryan Keech · Portland, US
• Nicholas G. Minutillo · Beaverton, US
• Suresh Vishwanath · Portland, US

Key dates

• Filing date: Mar 27, 2019
• Grant date: Jan 10, 2023
• Expiry date: May 9, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/121
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Integrated circuit structures having source or drain structures with phosphorous and arsenic co-dopants are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The first and second source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.