Ryan Keech
18Patents
1h-index
38Co-inventors
46Inventor score
Filing activity: Sep 26, 2018 → Jan 29, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11610889B2 | Arsenic-doped epitaxial, source/drain regions for NMOS | Electricity | 2 | Active |
| US11804523B2 | High aspect ratio source or drain structures with abrupt dopant profile | Electricity | 1 | Active |
| US11552169B2 | Source or drain structures with phosphorous and arsenic co-dopants | Electricity | 1 | Active |
| US11935887B2 | Source or drain structures with vertical trenches | Electricity | 1 | Active |
| US11164785B2 | Three-dimensional integrated circuits (3DICs) including upper-level transistors with epitaxial source and drain material | Electricity | 1 | Active |
| US11328988B2 | Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication | Electricity | 1 | Active |
| US12342574B2 | Contact resistance reduction in transistor devices with metallization on both sides | Electricity | 0 | Active |
| US12094881B2 | Arsenic-doped epitaxial source/drain regions for NMOS | Electricity | 0 | Active |
| US11929320B2 | Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication | Electricity | 0 | Active |
| US12288808B2 | High aspect ratio source or drain structures with abrupt dopant profile | Electricity | 0 | Active |
| US11482621B2 | Vertically stacked CMOS with upfront M0 interconnect | Electricity | 0 | Active |
| US12119387B2 | Low resistance approaches for fabricating contacts and the resulting structures | Performing Operations; Transporting | 0 | Active |
| US12266570B2 | Self-aligned interconnect structures and methods of fabrication | Electricity | 0 | Active |
| US12388011B2 | Top gate recessed channel CMOS thin film transistor and methods of fabrication | Electricity | 0 | Active |
| US11244943B2 | Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material | Electricity | 0 | Active |
| US11996404B2 | Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material | Electricity | 0 | Active |
| US12342611B2 | Source or drain structures with vertical trenches | Electricity | 0 | Active |
| US11973143B2 | Source or drain structures for germanium N-channel devices | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.