High voltage double-diffused metal oxide semiconductor transistor with isolated parasitic bipolar junction transistor region

US11552190B2 · kind B2 · utility

Assignee

• Analog Devices International Unlimited Company · IE

Inventors

• Edward John Coyne · Athenry, IE
• Alan Brannick · Raheen, IE
• John P. Meskell · Newport, IE

Key dates

• Filing date: Nov 19, 2020
• Grant date: Jan 10, 2023
• Expiry date: Nov 19, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/811

Abstract

A modified structure of an n-channel lateral double-diffused metal oxide semiconductor (LDMOS) transistor is provided to suppress the rupturing of the gate-oxide which can occur during the operation of the LDMOS transistor. The LDMOS transistor comprises a dielectric isolation structure which physically isolates the region comprising a parasitic NPN transistor from the region generating a hole current due to weak-impact ionization, e.g., the extended drain region of the LDMOS transistor. According to an embodiment of the disclosure, this can be achieved using a vertical trench between the two regions. Further embodiments are also proposed to enable a reduction in the gain of the parasitic NPN transistor and in the backgate resistance in order to further improve the robustness of the LDMOS transistor.