Implementing automatic rate control in a memory sub-system
US11556258B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2021 |
| Grant date | Jan 17, 2023 |
| Priority date | — |
| Expiry date | Jul 19, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device in a memory system identifies, while the memory device is in a first state condition, a plurality of workload conditions associated with the memory device, wherein the plurality of workload conditions comprise data reflecting a performance condition of the memory device. The processing device determines, while the memory device is in the first state condition, a host rate of a host system write performance for the memory device based on one or more workload conditions of the plurality of workload conditions. The processing device determines that one or more workload conditions of the plurality of workload conditions satisfies a first threshold criterion. Responsive to determining that the one or more workload conditions of the plurality of workload conditions satisfies the first threshold criterion, the processing device detects a change in a condition of the memory device from the first state to a second state. The processing device determines, while the memory device is in the second state condition, an adjusted host rate based on the host rate and a calculated adjustment value. The processing device uses the adjusted host rate to determine a credit consuming …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.