Configurable delay insertion in compiled instructions
US11556342B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2020 |
| Grant date | Jan 17, 2023 |
| Priority date | — |
| Expiry date | Nov 10, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for utilizing configurable delays in an instruction stream. A set of instructions to be executed on a set of engines are generated. The set of engines are distributed between a set of hardware elements. A set of configurable delays are inserted into the set of instructions. Each of the set of configurable delays includes an adjustable delay amount that delays an execution of the set of instructions on the set of engines. The adjustable delay amount is adjustable by a runtime application that facilitates the execution of the set of instructions on the set of engines. The runtime application is configured to determine a runtime condition associated with the execution of the set of instructions on the set of engines and to adjust the set of configurable delays based on the runtime condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.