Quantum code for reduced frequency collisions in qubit lattices
US11556411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2019 |
| Grant date | Jan 17, 2023 |
| Priority date | — |
| Expiry date | Oct 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/0852
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.