Patent · US Active

Scalable runtime validation for on-device design rule checks

US11556677B2 · kind B2 · utility

8Cited by

21References

18Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Furkan Turan · Leuven, BE
Patrick Koeberl · Hähnlein, DE
Alpa Trivedi · Hillsboro, US
Steffen Schulz · Darmstadt, DE
Scott J. Weber · Piedmont, US

Key dates

Filing date	Dec 23, 2020
Grant date	Jan 17, 2023
Priority date	—
Expiry date	Dec 23, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH04L9/0841
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, one or more multiplexors, and a validator communicably coupled to the memory. In one implementation, the validator is to: receive design rule information for the one or more multiplexers, the design rule information referencing the contention set; analyze, using the design rule information, a user bitstream against the contention set at a programming time of the apparatus, the user bitstream for programming the one or more multiplexors; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.