Erasing a partition of an SRAM array with hardware support

US11557335B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Martin Bernhard Schmidt · Stuttgart, DE
• Peter Altevogt · Ettlingen, DE
• Wolfgang Gellerich · Eppelheim, DE
• Juergen Pille · Stuttgart, DE
• Harry Barowski · Balingen, DE

Key dates

• Filing date: Jul 7, 2020
• Grant date: Jan 17, 2023
• Expiry date: Aug 30, 2040

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/4087
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The disclosure relates to an initialization circuit for initializing memory cells of a memory array including a common bit line. Individual memory cells are coupled to the common bit line of the memory array via at least one pass element of the individual memory cells. The initialization circuit is operable for receiving a set of partition addresses specifying the partitions, i.e. the memory cells to be initialized. The initialization circuit is operable for successively initializing one cell of the partitions to be initialized and iteratively initializing the remaining memory cells of the partitions to be initialized. A number of memory cells initialized simultaneously in one iteration increases from one iteration to another iteration. Initializing a certain memory cell comprises activating the pass element of the cell so that the memory cell is connected to the bit line. Further aspects relate to methods for initializing memory cells and semiconductor circuits.