Multi-level cell threshold voltage operation of one-selector-one-resistor structure included in a crossbar array
US11557342B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2021 |
| Grant date | Jan 17, 2023 |
| Priority date | — |
| Expiry date | Aug 17, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/826
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in electrical communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.