Self-adaptive program pulse width for programming 3D NAND memory
US11557346B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2021 |
| Grant date | Jan 17, 2023 |
| Priority date | — |
| Expiry date | Jun 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and techniques are described for detecting and compensating for a set of memory cells having a slow program speed, based on a comparison between the number of program loops used to complete programming for different data states. A program loop (PL) number is stored when programming is completed for memory cells of each assigned data state. The PL number of an nth state is then compared to the PL number of another state such as the n−1st state. If the difference between the PL numbers exceeds a threshold, the set of memory cells is considered to be slow programming and a compensation is triggered. The compensation can involve increasing the program pulse width in each remaining program pulse of the program operation. In another approach, the compensation can be triggered and subsequently deactivated in the program operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.