ATPG testing method for latch based memories, for area reduction
US11557364B1 · kind B1 · utility
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3References
19Claims
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Key dates
| Filing date | Jul 27, 2021 |
| Grant date | Jan 17, 2023 |
| Priority date | — |
| Expiry date | Jul 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.