Selective underfill assembly and method therefor
US11557491B2 · kind B2 · utility
0Cited by
9References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2019 |
| Grant date | Jan 17, 2023 |
| Priority date | — |
| Expiry date | Oct 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.