Systems and methods for detecting faults in an analog input/output circuitry
US11561255B2 · kind B2 · utility
1Cited by
3References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 15, 2021 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Apr 15, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes an input/output (I/O) circuit configured to receive a first signal and a second signal and a fault detection circuit. The I/O circuit includes an I/O terminal, an I/O buffer, and a pull resistor having a first terminal coupled to the I/O terminal. The fault detection circuit is configured to determine whether a predetermined number of toggles of the first signal occurs while the second signal is held at a constant logic state, assert a fault indicator when the predetermined number of toggles occurs, and negate the fault indicator when the predetermined number of toggles does not occur.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.