Refresh management for DRAM
US11561862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2020 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Dec 9, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller interfaces with a dynamic random access memory (DRAM). The memory controller selectively places memory commands in a memory interface queue, and transmits the commands from the memory interface queue to a memory channel connected to at least one dynamic random access memory (DRAM). The transmitted commands are stored in a replay queue. A number of activate commands to a memory region of the DRAM is counted. Based on this count, a refresh control circuit signals that an urgent refresh command should be sent to the memory region. In response to detecting a designated type of error, a recovery sequence initiates to re-transmit memory commands from the replay queue. Designated error conditions can cause the recovery sequence to restart. If an urgent refresh command is pending when such a restart occurs, the recovery sequence is interrupted to allow the urgent refresh command to be sent.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.