Pipelined micro controller unit
US11561883B2 · kind B2 · utility
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3References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2019 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Aug 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 3D NAND memory device is provided in which control is performed by two microcontroller units (MCU). During manufacture of the memory device, bug fixes required for the controller may be addressed using a software solution by which an instruction requiring correction in one of the two MCUs is replaced with a corrected instruction stored in a RAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.