Memory devices and methods of manufacturing thereof
US11563015B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2020 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Jan 13, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/25
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a first transistor. The first transistor includes one or more first semiconductor nanostructures spaced apart from one another along a first direction. Each of the one or more first semiconductor nanostructures has a first width along a second direction perpendicular to the first direction. The memory device also includes a second transistor coupled to the first transistor in series. The second transistor includes one or more second semiconductor nanostructures spaced apart from one another along the first direction. Each of the one or more second semiconductor nanostructures has a second, different width along the second direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.