Self-aligned gate edge and local interconnect
US11563081B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2020 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Aug 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0188
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.