FinFET structures and methods of forming the same
US11563120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2020 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Nov 12, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
Abstract
A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.