System and method for high reliability fast RAID decoding for NAND flash memories
US11563450B1 · kind B1 · utility
6Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Mar 13, 2020 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Mar 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/152
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flash memory system may include a flash memory and a circuit for decoding a result of a read operation on the flash memory using a first codeword. The circuit may be configured to generate an estimated codeword based on a result of hard decoding the first codeword and a result of hard decoding a second codeword. The circuit may be further configured to generate soft information based on the hard decoding result of the first codeword and the estimated codeword. The circuit may be further configured to decode the result of the read operation on the flash memory using the soft information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.