Ofir Kanter
27Patents
5h-index
17Co-inventors
62Inventor score
Filing activity: Jun 28, 2005 → Jun 26, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8539311B2 | System and method for data recovery in multi-level cell memories | Physics | 19 | Active |
| US8850296B2 | Encoding method and system, decoding method and system | Electricity | 17 | Active |
| US11563450B1 | System and method for high reliability fast RAID decoding for NAND flash memories | Electricity | 6 | Active |
| US11258466B1 | System and method for high reliability fast raid soft decoding for NAND flash memories | Physics | 6 | Active |
| US8276051B2 | Chien-search system employing a clock-gating scheme to save power for error correction decoder and other applications | Electricity | 6 | Active |
| US8607128B2 | Low power chien-search based BCH/RS decoding system for flash memory, mobile communications devices and other applications | Electricity | 5 | Active |
| US8972472B2 | Apparatus and methods for hardware-efficient unbiased rounding | Physics | 3 | Active |
| US11689219B1 | Method and system for error correction in memory devices using irregular error correction code components | Electricity | 3 | Active |
| US7516380B2 | BIST to provide jitter data and associated methods of operation | Physics | 2 | Active |
| US7539916B2 | BIST to provide phase interpolator data and associated methods of operation | Electricity | 2 | Active |
| US11016844B2 | Error correction code structure | Electricity | 1 | Active |
| US8458574B2 | Compact chien-search based decoding apparatus and method | Electricity | 1 | Active |
| US12210412B2 | Hard decoding methods in data storage devices | Electricity | 0 | Active |
| US7552366B2 | Jitter tolerance testing apparatus, systems, and methods | Electricity | 0 | Active |
| US12119075B2 | Efficient soft decoding of error correction code via extrinsic bit information | Physics | 0 | Active |
| US12009840B2 | Systems and methods of decoding error correction code of a memory device with dynamic bit error estimation | Electricity | 0 | Active |
| US12189476B2 | Soft error detection and correction for data storage devices | Electricity | 0 | Active |
| US12176924B2 | Deep neural network implementation for concatenated codes | Electricity | 0 | Active |
| US11513894B2 | Hard decoding methods in data storage devices | Electricity | 0 | Active |
| US12283972B2 | Method and system for error correction in memory devices using irregular error correction code components | Electricity | 0 | Active |
| US11693733B2 | Soft error detection and correction for data storage devices | Electricity | 0 | Active |
| US12095481B2 | Efficient decoding schemes for error correcting codes for memory devices | Electricity | 0 | Active |
| US12197283B2 | Efficient hard decoding of error correction code via extrinsic bit information | Physics | 0 | Active |
| US12050514B1 | Deep neural network implementation for soft decoding of BCH code | Electricity | 0 | Active |
| US12260129B2 | Tracking and updating read command voltage thresholds in solid-state drives | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.