Input/output voltage testing with boundary scan bypass
US11567130B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2020 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | Feb 1, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31724
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit device may include core circuitry, and a set of external interface buffer circuits coupled to the core circuitry. To improve test time and accuracy, as well as to simplify test procedures during voltage testing of the set of external interface buffer circuits, the integrated circuit device may include a test circuit and a combinational logic circuit coupled to the set of external interface buffer circuits. The combinational logic circuit is configured to combine a logic level of each of the external interface buffer circuits into a test signal, and the test circuit is configured to execute a voltage test on the set of external interface buffer circuits based on a logic level of the test signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.