Handling bad blocks generated during a block erase operation
US11567689B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Aug 5, 2021 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | Aug 5, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory component includes multiple fuses, a memory array having a multiple blocks, and control logic operatively coupled with the memory array and the plurality of fuses. The control logic is to perform operations including detecting a failure to completely erase a block of the plurality of blocks in response to an attempted erasure of the block; receiving a blow fuse command in response to the failure to completely erase the block; and blowing a fuse, of the plurality of fuses, coupled with the block, to make the block electrically inaccessible to the control logic in response to receipt of the blow fuse command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.