Layout structure for shared analog bus in unit element multiplier
US11567730B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2021 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | Jul 9, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4814
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A planar fabrication charge transfer capacitor for coupling charge from a Unit Element (UE) generates a positive charge first output V_PP and a positive charge second output V_NP, the first output coupled to a positive charge line comprising a continuous first planar conductor, a continuous second planar conductor parallel to the first planar conductor, and a continuous third planar conductor parallel to the first planar conductor and second planar conductor, the charge transfer capacitor comprising, in sequence: a first co-planar conductor segment, the first planar conductor, a second co-planar conductor segment, the second planar conductor, a third co-planar conductor segment, the third planar conductor, and a fourth coplanar conductor segment, the first and third coplanar conductor segments capacitively edge coupled to the UE first output V_PP, the second and fourth coplanar conductor segments capacitively edge coupled to the UE second output V_NP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.