Systems, methods, and apparatuses for tile load
US11567765B2 · kind B2 · utility
6Cited by
89References
20Claims
0Family size
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Key dates
| Filing date | Jul 1, 2017 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | Jul 1, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/455
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.