Read-out circuit and read-out method for three-dimensional memory
US11568931B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2017 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | Apr 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read-out circuit and a read-out method for a three-dimensional memory, comprises a read reference circuit and a sensitive amplifier, the read reference circuit produces read reference current capable of quickly distinguishing reading low-resistance state unit current and reading high-resistance state unit current. The read reference circuit comprises a reference unit, a bit line matching module, a word line matching module and a transmission gate parasitic parameter matching module. With respect to the parasitic effect and electric leakage of the three-dimensional memory in the plane and vertical directions, the present invention introduces the matching of bit line parasite parameters, leakage current and transmission gate parasitic parameters into the read reference current, and introduces the matching of parasitic parameters of current mirror into the read current, thereby eliminating the phenomenon of pseudo reading and reducing the read-out time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.