Memory plane access management
US11568933B1 · kind B1 · utility
3Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2021 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | Aug 27, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes identifying a target plane in respective planes of a memory die in a non-volatile memory array and identifying, from blocks of non-volatile memory cells coupled to a common bit line in the target plane, at least one target block in the target plane. The method further includes performing an operation to disable at least one gate associated with the at least one target block to prevent access to the blocks of non-volatile memory cells coupled to the common bit line in the target plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.