Semiconductor device
US11569128B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2021 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | May 16, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.