Semiconductor package and method of forming the same
US11569146B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2017 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | May 19, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01Q21/065
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments may provide a semiconductor package. The semiconductor package may include a semiconductor chip, a first mold compound layer at least partially covering the semiconductor chip, and a redistribution layer over the first mold compound layer, the redistribution layer including one or more electrically conductive lines in electrical connection with the semiconductor chip. The semiconductor package may additionally include a second mold compound layer over the redistribution layer, and an antenna array over the second mold compound layer, the antenna array configured to be coupled to the one or more electrically conductive lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.