Integrated memory coplanar transmission line package having ground path that brackets data path to extend memory speeds
US11569161B2 · kind B2 · utility
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1References
8Claims
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Key dates
| Filing date | Jan 29, 2019 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | Jun 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, that comprises a bumpout region on a first surface of the package substrate, and a pin region on a second surface of the package substrate. In an embodiment, a data path from the bumpout region to the pin region is included in the electronic package. In an embodiment, a ground path brackets the data path from the bumpout region to the pin region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.