Semiconductor package and method of fabricating the same
US11569201B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Oct 25, 2021 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | Oct 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.